Comparative Study of Si3N4 and HfO2/Si3N4 Stacked Trapping Layer on Junctionless Poly-Si Flash Memory Device

Effects of Si3N4 trapping layer (NTL) and HfO2/Si3N4 bandgap-engineered trapping layer (BETL) on junctionless (JL) polycrystalline-based flash memory devices are investigated in this work. The programming speed is clearly improved by BETL but the erasing speed is only slightly improved. JL device with BETL performs better retention characteristics since the conduction band offset between Si3N4 and HfO2 can reduce the leakage of trapped charges in HfO2. The endurance characteristics of BETL sample is similar to that of NTL one, because both JL devices are less sensitive to interface state generation. Introduction: For lower cost and higher device density, polycrystalline-Si (poly-Si) flash memory cell technology is regarded as a promising candidate for three-dimensional (3-D) NAND flash architecture. Since the doping control of source/drain (S/D) junction formation is difficult in 3-D architecture, an innovative junction formation process is necessary. A JL device is proposed by homogeneously doping S/D and channel, which is easily fabricated and free from S/D junctions [1]. Most studies about JL flash devices are based on NTL. The programming speeds of JL devices are improved by the electron-rich channel, but their erasing speeds are sacrificed due to the less hole generation. Effects of HfO2/Si3N4 BETL on bulk planar devices and NW channel devices were reported to obtain better operating speeds and reliability performances [2]. However, these studies are only based on inversion mode flash devices. In this work, comparisons between NTL and HfO2/Si3N4 BETL on JL flash devices with nanowire (NW) channels are studied. Experimental: NTL and BETL devices are both fabricated on 6-inch Si (100) wafer. Firstly, four SiO2 dummy fins with a height of 100 nm are formed by I-line lithography and reactive ion etching (RIE) process on Si3N4 buried layer. An 100-nm thick amorphous-Si is then deposited and transferred into polySi by solid-phase crystallization (SPC) process at 600 °C for 24 hours. Both samples are sent to perform Phosphorous implantation (at 30 keV to a dose of 1×10 cm) and activation (900 °C for 30 s). S/D region is defined on two ends of dummy fins for all samples. Eight spacer NW channels are consistently formed with S/D region by precise RIE process control; SiO2 dummy fins are removed by diluted HF to complete active region. 3.5 nm SiO2 is grown as tunneling layer for both samples. 6 nm Si3N4 is deposited as NTL for one sample; 3 nm Si3N4 and 7 nm HfO2 are sequentially deposited as BETL for another one. 18 nm Al2O3 is deposited as blocking layer, followed by TiN gate deposition. After gate region formation, both samples are sent to go through passivation and metallization processes, completed after sintering at 400 °C for 30 min. Results and Discussion: Fig. 1 is the transmission electron microscopy (TEM) image of BETL device. The dielectric thicknesses are indicated and the width of a NW is ~25 nm. The transfer characteristics at VDS = 0.5 V are shown in Fig. 2. The on-currents of both devices don’t increase with gate bias, because the on-current of JL device is most related with the effective channel doping and less dependent on the increasing gate bias. Fig. 3 shows the programming speeds at VGS = 14 V. The programming speed of JL device is improved by BETL due to the high trap density and lower conduction band level of HfO2 as the band diagram indicates in Fig. 4 [2]. Fig 5 shows the erasing speed comparison of devices with a previous window of 2.5 V. The erasing speed is only slightly improved by BETL. It is because holes are less generated for JL device. Fewer holes are blocked by the barrier of HfO2 during erasing operation such that the function of BETL is minor. Fig. 6 shows the retention characteristics tested at room temperature and 85 °C with a previous window of 2.5 V. The JL device with BETL performs better charge storage ability at both test conditions, which is because the conduction band offset between Si3N4 and HfO2 can reduce the leakage of trapped charges in HfO2. The endurance characteristics are shown in Fig. 7. Both devices perform good and similar cycling endurance because JL device is less sensitive to interface states due to the bulk conduction mechanism during cycling test. ISDRS 2013, December 11-13. 2013 Conclusions: Compared with NTL device, the programming speed of JL device is improved by BETLdue to the lower conduction band level of HfO2. The improvement of erasing speed by BETL is littlesince the function of BETL is not obvious when fewer holes are injected. Retention characteristics of JLdevice are improved by BETL due to the reduced charge leakage by the conduction band offset betweenHfO2 and Si3N4. The endurance performance of JL device with BETL is similar with that with NTL. It isbecause JL device is less sensitive to interface states due to its bulk conduction mechanism. References[1] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A.Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,”Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.[2] C. Y. Chen, K. S. Chang-Liao, K. T. Wu and T. K. Wang, "Improved erasing speed in junctionlessflash memory device by stacked trapping layer," IEEE Electron Device Lett., vol. 34, pp. 993-995, Aug.2013. Fig. 1 Cross-section TEM image of JL device withBETL.Fig. 2 Transfer characteristics of NTL andBETL devices. Fig. 3 Programming speedcomparison of NTL and BETLdevices.Fig. 4 Schematic energy banddiagram of JL device with BETLat VGS = 14 VFig. 5 Erasing speed comparisonof NTL and BETL devices. Fig. 6 Retention characteristics of NTL and BETLdevices measured at different temperatures.Fig. 7 Endurance characteristics of NTL andBETL devices with an initial window of 2 V.